Technical Field
Embodiments described herein are related to reliability checking during the design of integrated circuits.
Description of the Related Art
Semiconducting chips, or integrated circuits, include a dense array of narrow, thin-film metallic conductors that serve to transport current between the various devices on the chip. These metallic conductors are called interconnects or “wires.” Interconnects are subject to wear-out mechanisms over the lifetime of the product caused by, among other things, electromigration and Joule heating from current flowing through these wires. Healing effect may also be considered when checking for potential electromigration issues.
Electromigration is generally considered to be the result of momentum transfer during current flow from the electrons to the ions in the lattice of the interconnect material. The momentum transfer may cause the ions to move into the wires causing grain size change and wire resistance increase, as well as voids or hillocks that can cause opens or shorts in the wires. The opens and shorts generally lead to catastrophic failure of the integrated circuit. Interconnect wear out is a strong function of the wire temperature and average current through the wire. Higher temperatures correlate to faster interconnect failures (and thus shorter lifetimes for the integrated circuit). Similarly, higher currents correlate to faster interconnect failures. For this reason, based on expected operating temperature conditions, maximum current limits are followed in the design of the integrated circuit, in order to reduce failure from electromigration and thus provide for longer product lifetimes.
Joule heating is the process of the wire heating during current flow. This temperature rise due to Joule heating accelerates electromigration. Accordingly, Joule heating is also accounted for when checking the electromigration current limits (in addition to the expected operating temperature of the integrated circuit). The heat generated by a selected wire can also propagate to adjacent wires and increases the overall temperature of the chip. For this reason, current density is limited to reduce the amount of wire temperature rise and associated acceleration of electromigration. For example, a maximum budget for Joule heat may be established for a given integrated circuit, and the temperature rise due to the Joule heat is added to the expected operating temperature to determine the temperature to be used for electromigration checks.
AC currents may have symmetric current waveforms of both polarities (negative/positive). For A/C current waveforms, the electromigration damage due to the current in one direction may fully or mostly compensate for the opposite polarity current, assuming both polarities of currents occur at the same operating temperature (the “healing effect”). Accordingly, signal wires in digital circuits that have symmetric waveforms may not display significant electromigration but the amount of Joule heating can still be an issue. For example, integrated circuits that implement complementary metal-oxide-semiconductor (CMOS) technology have symmetrical currents from the positive power supply node to signal wires, and from the signal wires to ground. Power supply interconnects (e.g. VDD and VSS, or ground) on the other hand, may have mostly unidirectional currents and are subject to both electromigration and Joule heating effects.
Due to continuing miniaturization of very large scale integrated (VLSI) circuits and the push for higher performance, interconnects are subject to increasing current densities. Accordingly, integrated circuit foundries (which manufacture the integrated circuits) provide guidelines for maximum currents to the integrated circuit designers. The maximum current guidelines account for electromigration and Joule heating. Electronic design automation (EDA) tools and flows are available for designers to ensure current limits meet requirements. Typically, separate design flows are run to check electromigration for power grid wires and signal wires as they are subject to different constraints.
If the current density limit is exceeded for a given wire, the designer makes changes to the wire to bring the current density within the limits. For example, the designer may increase the wire width of the give wire, or may reduce the amount of current through the given wire by reducing the current capacity of the circuitry driving the wire. Both these actions may have the side effect of reducing the performance and/or increasing the area of the design. Overly-conservative limits from the foundry may thus reduce performance and/or increase design effort and time.
EDA tools assume that the full temperature rise due to Joule heating is added to the product operating temperature to set the electromigration current density limits for the integrated circuit. This assumption is pessimistic: the entire chip temperature may not rise due to the Joule heating; but rather the temperature may increase only locally where the wire current is close to the limit. In addition, the amount of Joule heating of a selected wire is a strong function of the surrounding wires and current density flow in adjacent wires. The foundry guidelines are set on worst case configuration: multiple wires at minimum space carrying the worst case current density without metal running below and above. In these conditions, the wires may be subject to more severe temperature rise. If the worst case configuration does not accurately represent a given wire, the limit is pessimistic, causing unwarranted design effort, increasing area for the design on the integrated circuit, and increasing power consumption.